1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method for forming an LDD structure and a heavily doped source/drain structure on a semiconductor substrate.
2. Background of the Invention
A metal oxide semiconductor field effect transistor (MOS transistor) comprises a semiconductor substrate, in which a source/drain region and on which a gate structure are formed. MOS transistors can be either N-channel devices or P-channel devices. In CMOS (complementary metal oxide semiconductor) technology, both N-channel devices and P-channel devices are employed to form logic circuits.
Lightly doped drain (LDD) transistors having an LDD region inside the heavily doped source/drain regions are widely used. FIGS. 1a to 1d illustrate, in cross-section, a portion of a semiconductor device as it undergoes conventional processing steps in sequence for making an LDD MOS transistor.
Referring to FIG. 1a, a gate oxide layer 2 and a polysilicon layer 3 are, in this order, formed on a semiconductor substrate 1. The gate oxide layer 2 and the polysilicon layer 3 are etched using a photolithography process so that a gate structure 21 is formed as shown in FIG. 1b. Subsequently, an LDD region 4 is formed by doping the substrate 1 with a dopant of either N-type or P-type impurities using low levels of implant energy while using the gate structure 21 as a mask as shown in FIG. 1b.
Following the above, referring to FIG. 1c, an insulating layer 5' is deposited on the substrate 1 using an LPCVD (low pressure chemical vapor deposition) process. Then, the insulating layer 5' is anisotropically etched to form an insulating spacer 5 on the sidewall of the gate structure 21. Next, a dopant of the same impurity type as the LDD region 4 is introduced, using high levels of implant energy, into the substrate 1 while both the gate structure 21 and the insulating spacer 5 are used as a mask. A heavily doped source/drain region 6 is thus formed as shown in FIG. 1d.
Finally, although not shown in the drawings, an insulating layer is deposited on the substrate 1 and is then etched to form contact holes through which electrodes contact both the polysilicon layer 3 of the gate structure 21 and the source/drain region 6.
In the above described prior art process, with the increasing miniaturization of semiconductor devices, it has become more difficult to form a gate structure pattern using a masking process as described above, particularly when the degree of integration is less than 0.3 .mu.m.
In addition, in the above described process, because the LDD region is formed after the formation of the gate structure, it is necessary to configure the insulating spacer around the gate structure which increases the critical dimension, i.e. the length, of the gate structure. The increase in the critical dimension of the gate structure limits the degree to which the semiconductor device can be integrated.